RTL Design Verification Engineer
Role Overview:
Responsible for verifying RTL designs using System Verilog and UVM to ensure design correctness and functionality before chip fabrication.
Key Responsibilities:
- Develop test plans and UVM-based test suites
- Conduct IP, module, subsystem, and So C-level verification
- Perform testbench linting and formal assertion checks
- Verify low-power features and create emulation and FPGA prototypes
Skills Required:
- Strong proficiency in System Verilog and UVM
- Experience in formal verification and low-power design validation
- Familiarity with emulation models and FPGA prototyping
- Ability to develop scalable and reusable verification environments
